1. Field of the Invention
This invention generally relates to methods and systems for altering at least one parameter of electrical testing for a wafer based on information for one or more characteristics of a physical version of the wafer generated by performing an inline process on the physical version of the wafer.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
At some point after fabrication of integrated circuits (ICs) on wafers, the ICs are electrically tested for quality control purposes. The testing may be performed to determine if a chip passes or fails electrical performance requirements. In addition, electrical testing may be performed to determine why a chip is performing the way that it is. Such testing may be used to determine information about the process that was used to fabricate the chip. In addition, such testing may be used to determine information about the chip itself (e.g., if the design of the chip is causing problems for the production).
Adaptive electrical testing practices are in place and being used today. However, they are primarily driven by real time signals from the electrical testing floor regarding the health of various components of the test infrastructure. These current practices generally do not consider inline wafer-related data in deciding the direction and intent of dynamic adaptation. In some particular cases, specific IC vendors may have chosen to consider some of the vast inline wafer-related data to drive adaptation choices. But the detailed granularity of defect parameters against specifications and stability data attributes offered by today's inline inspection, metrology, and tool monitoring systems is not linked to testing in any of the industry's adaptive testing practices.
Older methods of electrical testing are able to look at the inline defect data at a full wafer or an individual die level where this is a mostly manual decision driven by an engineer's judgment. These methods typically trigger a binary switch from a less intensive pass/fail type of test plan with a relatively small number of individual test vectors to a more intensive debug type of test plan with a relatively large number of individual test vectors. In cases of relatively high defect levels or metrology shifts reported by a fab, the test engineers can consider one of the two following approaches.
In the first approach, the electrical testing may involve testing the entire wafer with the pass/fail test plan and then 1) ink-dotting the failed dies for scrapping without any further testing, or 2) sending the ink-dotted dies for failure analysis. Failure analysis engineers look for any correlation between failed dies and the reported inline defect locations or (much less frequently) metrology values to guide root cause determination. If the inline data is not helpful, then the failure analysis engineer may also invoke a second test within a debug test plan. As the name indicates, the debug test plan is aiming for electrically localizing the failure within the device circuitry. However, in some cases, the debug test plan may indicate the die to be conditionally good and suitable for only a limited set of functions. Such dies could then be labeled as “good” for sale into a different, less stringent market, e.g., speed binning of processor chips.
In the second approach, during yield ramp, it is quite common to skip the pass/fail test plan on a few sampled wafers and send them directly through the debug test plan in offline mode. These wafers are typically also singled out for defect inspections and metrology at critical patterning layers during wafer fabrication.
In either approach, the contents of both the test plans have been fixed ahead of time. The pass/fail test plan operates on a “stop on first fail” prescription, which saves some test time per die by avoiding continued application of subsequent tests from the complete plan, once a die has failed a certain test. However, this test time reduction comes at the cost of any ability to localize the failures within the device circuitry. Thus, there is minimal guidance from such testing for any failure analysis purpose.
The debug test plan is designed to test the circuitry with a finer resolution and coverage such that when the test data is collected it allows triangulation of a likely failure location through comparison of observed and ideal test responses. There is a diminishing return with increasing number of tests and typically the actual number of tests is decided based on a balance of resolution and test time.
Both of the approaches described above are time consuming and require a production wafer to be pulled offline for additional testing. This is not an overhead that test engineers willingly accept. Any methodology that takes away some or all of this test time overhead should be very appealing to test engineers.
Accordingly, it would be advantageous to develop methods and systems for determining one or more parameters for electrical testing of a wafer that do not have one or more of the disadvantages described above.